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The application of activity-based costing (ABC) to drive cost reduction efforts for a new IC product line
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http://ieeexplore.ieee.org/xpl/freea...rnumber=588240

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على العموم ما هو موضوع حقيقة في الملف المرفق أعلاه هو abstract، وقد بحثت بواسطة ISBN الذي هو
Print ISBN: 0-7803-2053-0

والخاص بـ : : Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI

وكانت النتائج : 79 مقال (من هذل المؤتمر الذي كان في عام 1994) من بينهم المقال المطلوب وعلى العموم هذه هي (يمكن تحميلها كلها، حيث تشاهد حجم الملف وكما ترى مقالك المطلوب موجود في هذه النتائج وحجمه 48 Ko أي حوالي صفحة مع العلم أنه full text أي مقالك موجود في صيغة ورقية وليس إلكترونية...هذه النتائج (غير مرتبة جيدا) لعل هناك ما يشابه بحثك المطلوب ربما (لا أظن ذلك) ومن ثم يمكنني تحميل ما تريد من هذه القائمة المتعلقة بنفس ISBN

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Analysis of the effects of cross-field defocus on the photolithographic process window

Pelligrini, J.C.; Sager, C.B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588288
Publication Year: 1994

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Summary form only given. The focus-exposure process window has become an accepted standard for the characterization of stability of a photolithographic process. The process window is defined as a rectangular region in the focus-exposure plane where the process of interest is considered to perform within specifications (typically ±10% of target CD). The width of the box identifies the depth-of-focus and the box height represents the exposure latitude. Recent studies (Capsuto SPIE 1992, et al.) have shown that the defocus conditions that exist across a typical stepper exposure field can significantly impact DC performance. The proper characterization of the true process performance requires analysis of the common process window or “common corridor” which takes into account variable conditions that exist in non-laboratory environments. This study utilized a defocus map for a state of the art I-line stepper, obtained using an innovative focus monitor based on phase-shift mask technology. This defocus map was used to derive sampling plans for both real and simulated analysis based on the common corridor technique. This method resulted in a highly realistic estimate of the photolithographic process stability Read More»
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Sub 0.5 μm TCP metal etching in the ASTC

Christie, R.; Burns, S.; Grewal, V.S.; Spuler, B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588254
Publication Year: 1994

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Summary form only given, as follows. The IBM Advanced Technology Center (ASTC) has alliances with the Siemens Corporation and Toshiba for 64M and 256M DRAM process development, state of the art equipment in a state of the art facility, has allowed for quick development of processes for these technologies. High density DRAM technologies have moved metal etching into the sub 0.5 μm regime. These smaller geometries place demanding requirements on metal etch processing. With an increase in wafer size and pattern density, it becomes increasingly difficult to produce uniform profiles across a wafer. Unlike other films, metal etching requires post etch treatment to prevent the onset of corrosion. In a manufacturing environment, low cost of ownership and good tool reliability are essential. This paper discusses sub 0.5 μm aluminum etching in a 200 mm LAM TCP 9600 Etch Chamber and post etch wafer treatment. Chemistries, powers, and pressures have been optimized to produce higher selectivities (<5:1) to photoresist, less RIE lag (<15%), and more uniform profiles across a wafer, better particle control and the extended life of etch tool hardware with these parameter optimizations are also discussed Read More»
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Estimating the effect of contamination-induced leakage current in view of DRAM architectural trends

Schmid, J.R.; Parks, H.G.; Craigin, R.; Schrimpf, R.D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588261
Publication Year: 1994 , Page(s): 241 - 250

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Due to new memory-cell architectures, the leakage-current requirements for semiconductor memories will become less stringent with increased levels of integration. The implication of these requirements with regard to allowable metallic contamination levels is investigated with a one-dimensional model based on Shockley-Read-Hall generation-recombination. The model was developed to predict leakage-current in carrier-depleted regions as a function of basic process and metallic contaminant parameters. As device dimensions are reduced, transition metal homogeneous contamination in process chemicals can be an important source of generation-recombination centers that result in the dominant generation-current in the space-charge region. The model allows an estimation of an upper bound for transition metal contamination in advanced processes and is applied for DRAM leakage predictions. Using the model, it is demonstrated that the trend toward lower leakage-current density requirements reverses after the 64-Mbit generation DRAM as a result of memory-cell architecture trends which significantly reduce the space-charge volume Read More»
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Optimizing stepper mix to combat rising fab costs

Shafer, T.; Bigelow, M.G.; Greeneich, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588251
Publication Year: 1994 , Page(s): 215 - 219

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A mix/match strategy using high throughput lower-cost noncritical steppers combined with more expensive critical layer steppers is an excellent way to combat escalating equipment costs and increase capital productivity as well as lower operating costs. To maximize capital productivity over a long term and ensure return on investment it is important to buy enough performance for several generations of devices, while still minimizing the price/throughput ratio. Convincing arguments in this paper present the strategy of using 5x compatible non-critical steppers with high performance to support a strategy of achieving multiple generations of design rules with one equipment set. In addition the 5x stepper has a favorable price/throughput ratio when compared with 5x critical steppers. Finally, for fab managers, the practical logistics of manufacturing operations favors a choice of 5x compatibility when the issues of stepper capacity utilization, reticle compatibility, operator training, engineering process knowledge, spare parts and service engineering are considered Read More»
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Failure modes and effects analysis (FMEA) system deployment in a semiconductor manufacturing environment

Whitcomb, R.; Rioux, M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588224
Publication Year: 1994 , Page(s): 136 - 139

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Failure Modes and Effects Analysis (FMEA) is a systematic, learning retention vehicle originally developed by Ford Motor Company in the 1970s to aid the engineer in assessing potential failure modes and design in risk prevention measures for the automotive industry. This same approach can be applied, in much the same fashion, to the semiconductor manufacturing industry and result in retained learnings and a ranked priority of fab and die yield improvement activities. The FMEA system, as it is being applied to a National Semiconductor fab consists of a series of information templates that properly documents relevant information for each major processing step of each major process technology. This paper describes this FMEA system as it has been modified for use by National Semiconductor. The FMEA information template is detailed and the development and implementation approach on several of National Semiconductors major process technology flows is reviewed. The fit of the FMEA tool in the total process control scheme is discussed. In addition, specific examples of completed FMEAs for specific fabrication processing steps are presented along with actions taken to minimize calculated risk factors Read More»
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Nondestructive, at-line measurement of dielectric constant for VLSI intermetal dielectrics

Taylor, K.J.; Bruton, G.A.; Luo, D.; Kawski, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588255
Publication Year: 1994 , Page(s): 225 - 228

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Shrinking VLSI metallization schemes require new intermetal dielectrics (IMD) with low dielectric constant, K. Materials being considered are doped glasses, polymers, porous material and composites. Both the magnitude and the variability of the dielectric constant must be measured for these new dielectrics, hence, a new need to make reliable, accurate and cost-effective at-line measurements of the dielectric constant has emerged. We have developed a technique using commercially available, non contact capacitive probe and spectral ellipsometry tools to measure K to an accuracy of better than 5% at K<4.0. The accuracy and measurement system error improves as K decreases, so that measurements at K=2.0 should be accurate to 2% Read More»
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Current and future trends in microcontamination research

Blewer, R.S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588200
Publication Year: 1994 , Page(s): 83 - 86

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Because contamination can fatally flaw any process step in integrated circuit manufacture, contamination control is critically important to the yield and reliability of increasingly complex semiconductor devices. As industry strives to keep pace with rapidly shrinking feature sizes and as chip areas approach two square inches within the next ten years, stronger emphasis must be placed on contamination issues to achieve acceptable yields. The most critical research needs and requirements in contamination free manufacturing (CFM), as highlighted by the National Semiconductor Roadmap for Semiconductors, will be considered in this paper, with details and suggestions about seven important areas for research. A discussion of selected active CFM research activities and results are included, together with a list of several areas where additional research efforts should be initiated to meet future CFM Research Roadmap requirements Read More»
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Enhancing lithography for 1.0 micron and larger designs

Levine, A.L.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588263
Publication Year: 1994 , Page(s): 251 - 256

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The market for integrated circuits with feature sizes above 1.0 μm continues to play a tremendous role in the overall IC market. These circuits are built in highly competitive environments. In order to successfully compete, manufacturing costs must be optimized. A limited number of new wafer fabs are being built for >1.0 μm designs; most additional capacity in this area comes from facilities that are upgraded. This paper evaluates the cost of ownership of the exposure tools that serve this market. Several costs are evaluated, including labor, maintenance, facilities, reticles/masks and capital. Issues unique to existing facilities, such as continuing production while changing equipment, are also addressed. Technology considerations, including yield and extendability, are discussed. Results indicate that lithography systems can be designed that are highly cost effective and efficiently implemented in an upgrade environment Read More»
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Defect density reduction in tungsten deposition and etchback

Anderson, B.; Berezin, A.; Emami, I.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588275
Publication Year: 1994 , Page(s): 279 - 281

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An in-line defect density monitor was developed to measure the defect contribution for tungsten deposition and etchback. By continuously monitoring the processes, a number of defect generating mechanisms were discovered in both deposition and etch systems. By targeting improvements in equipment, processes, and maintenance, a factor of ten improvement was realized on the integrated monitor. The improvements also resulted in improved product yield and eliminated low yield excursions Read More»
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Comparison of the applications of process simulations and FMEA: two case studies

Tripathi, S.; Shankar, S.; Moghadam, F.; Garcia-Colevatti, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588226
Publication Year: 1994 , Page(s): 140 - 143

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In manufacturing it is imperative to control defect densities and film properties within unit process modules. Often, however, a lack of detailed characterization on cutting edge processes can hinder effective troubleshooting when problems do occur. We intend to highlight simple problem solving methodologies such as the Failure Modes and Effects Analysis (FMEA) that can be applied to a wide range of everyday problems that occur on all process modules. We provide two real life cases where the advanced and complex Finite Element Modeling (FEM) of the Navier Stokes Equation and the FMEA yielded identical results. The first case is that of contamination to the wafer backside that occurred in a CVD tungsten system and resulted in depressed yield, and equipment downtime in all downstream process modules. Process simulations at different settings of gas flow rates and pressure identified a process window where wafer backside contamination could occur. Subsequently an FMEA yielded identical results for the root cause. Within this case we present all possible failure mechanisms, review the methodologies used for risk assessment analysis, material dispositioning criteria and explain the procedures put in place to detect and eliminate future backside contamination. In the second case we report analysis of excessive downtime due to poor film uniformity that occurred from upgrading a CVD tool from 6" to 8". The differences between the 6" and the 8" chambers were analyzed using process modeling and FMEA Read More»
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The application of activity-based costing (ABC) to drive cost reduction efforts for a new IC product line

Naguib, H.; Bol, I.; Lora, J.; Chowdhry, R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588240
Publication Year: 1994

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Summary from only given. Activity-Based Costing (ABC) is a process which enables the assignment of costs to products based upon the use of resources in the creation or manufacture of the product. This paper presents a case study on the application of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The study was performed in six phases: forming the ABC team; developing the ABC model; costing the product line; planning cost reduction efforts; implementing cost reduction; and evaluating results. The ABC management team efforts resulted in significant reduction in the manufacturing costs of the new product line. In addition, the ABC model demonstrated the sensitivity of the cost per wafer to such parameters as composite yield, production volume, utilization rate of existing equipment, and the cost of purchasing of new equipment Read More»
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Self-directed work teams

Winter, R.A.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588220
Publication Year: 1994 , Page(s): 123 - 125

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This paper describes the effort and the success derived from implementing self-directed work teams at IBM's semiconductor manufacturing facility in Essex Junction, Vermont. Using the self-directed work team approach, traditional departments are subdivided into teams. Weekly team meetings are conducted to determine measurements for baselining improvement over time. Each team assumes responsibility for its own business strategy. Managers assume the role of coaches, consulting with individual teams and advising each on the path it should take to succeed. Technical people work with manufacturing personnel rather than directing them. Common goals are set and decisions made with the cooperation of the team. Carefully defined measurements provide motivation that encourage empowerment and group responsibility. This approach helps improve both team bonding and morale. With strong support from management, self-directed teams enable individuals to play an important role in the operation of their business and in defining customer needs Read More»
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Supplier Excel Teams (SETs)

Fearon, P.A.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588259
Publication Year: 1994 , Page(s): 237 - 239

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This paper describes the team model, design, mission, roadmap and sustaining process of the Silicon Supplier Excel Team (SET) used by National Semiconductor's Digital Logic high volume fab in South Portland, Maine. Historically, procurement activities have been silo oriented, with each department in the procurement process concentrating only on their portion of the process. Process engineering wrote the specification and did not communicate with purchasing who in turn only looked for the lowest price while Q/A only interacted with process engineering if there was a problem. This technique is no longer acceptable under the new team culture of National. In order to provide the fab with the highest quality, lowest cost of ownership materials. A new system of materials procurement is deemed to be necessary. The SET concept embodies all of the principles of our in-house cross-functional teams but takes it one step further and includes the supplier as a team member Read More»
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Future directions in controlling particle contamination in semiconductor integrated circuit manufacturing: an industry survey

Rappa, M.A.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588202
Publication Year: 1994 , Page(s): 87 - 91

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Rapid progress in integrated circuit technology and the rising cost of wafer fabrication makes contamination control a critical issue in the semiconductor industry. This paper describes the results of an international survey of 750 contamination control specialists in the semiconductor fabrication and equipment industry. The purpose of the survey is to assess (1) the current problems in sub-micron IC manufacturing; (2) emerging technologies to deal with these problems; and (3) the potential of new solutions, such as minienvironments, to emerge as a significant alternative approach to conventional cleanrooms. The latter question is of particular interest. The survey examines current opinion on minienvironments and identifies the major obstacles toward the adoption and implementation of the standard mechanical interface (SMIF) Read More»
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Real time, in situ measurement of film thickness with reflexion supported pyrometric interferometry (RSPI)

Boebel, F.G.; Hertel, B.; Moller, H.; Preiss, W.; Ritter, G.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588285
Publication Year: 1994 , Page(s): 311 - 315

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Real time, in situ measurement of film thickness is of crucial importance for many manufacturing processes of high-end electronic and opto-electronic devices. Most in situ process control strategies depend heavily on large data bases of process and material parameters. With RSPI film thickness and temperature are evaluated together with optical material parameters in real time using the measured data only. Material and process parameters need not to be known for evaluation. In this paper we concentrate on real time, in situ determination of film thickness and optical constants by RSPI. Temperature measurements by RSPI are discussed elsewhere. As far as the physical measurement principle for film thickness is concerned, RSPI is identical to similar intensity based monochromatic interferometric methods like Dynamical Optical Reflectivity (DOR), etc. The main progress made by RSPI compared to similar inteferometric methods concerns the evaluation algorithms, which made RSPI the only intensity based measurement approach so far suitable for in situ film thickness monitoring of multi-layer stacks and real time in situ evaluation of composition (via determination of optical constants). RSPI has been proven to be a suitable method for in situ monitoring of growth in silicon processing. Data from Si(1-x) Gex Rapid Thermal Chemical Vapour Deposition (RTCVD) growth on Si wafers as well as poly-Si on a Si wafer coated with 200 nm of Si3N4 are presented. Further experiments have been carried out during wet silicon oxidation. In most cases thickness resolution has been better than 0.5 nm. The in situ determination of optical constants by RSPI agrees within 1% with literature values Read More»
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Design of single wafer future logic fabs

Castrucci, P.; Griffin, J.; Williams, M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588151
Publication Year: 1994 , Page(s): 1 - 6

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We will describe several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, we will compare four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less Read More»
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ASMC 94 Invited Speakers


Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588290
Publication Year: 1994 , Page(s): 323 - 334

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Early LSI mass production - fast yield improvement and Si debugging

Tsujide, T.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588223
Publication Year: 1994 , Page(s): 130 - 135

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Failure analysis plays a very important role in the early introduction and fast yield improvement of new generation LSI's. We have developed novel failure analysis technologies including an expert-system-based memory cell failure cause identification system, which is linked to a particle or defect monitoring tool, as well as failure location isolation systems for memory peripheral circuitry and logic LSI's. This paper reviews all these technologies and introduces some examples of their implementation Read More»
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The cost of ownership

Rahaim, P.T.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588241
Publication Year: 1994 , Page(s): 186 - 188

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IBM's semiconductor manufacturing facility in Essex Junction, Vermont, uses a “cost-of-ownership” (COO) program to analyze every operation in its production lines. With a customized COO modeling program, we can determine the cost for each manufacturing operation. Pareto data analyses can highlight key areas where improvements can be most beneficial; the data gives the cost of various items, listed from the highest to lowest cost and the percentage value of each item. This modeling program has been vary helpful and enlightening. It not only identifies the major items significantly increasing costs, but also quantifies the impact each change or improvement will have on individual operations. The methodology of this program has enabled us to drive down the cast of our semiconductor products while maintaining a high degree of quality and reliability. Information obtained from the COO program is being used to select future products for the IBM Microelectronics product menu Read More»
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Synchronous flow management (SFM) principles in the manufacturing of discrete power devices

Murphy, R.E., Jr.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588239
Publication Year: 1994 , Page(s): 179 - 184

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Harris Semiconductor's Mountaintop, PA facility is incorporating Synchronous Flow Management (SFM) principles in its manufacturing of Discrete Power Devices. Synchronous Flow Management (SFM) is a science of management that addresses the total flow of an organization. When employed, its economic impact is fast, direct, and often enormous. By managing the constraints that control all organizations, the achievement of the “goal” is possible. The goal in all organizations is to make money now and in the future. This paper discusses structural, managerial and behavioral constraints within the Mountaintop facility that had to be identified and controlled to implement a synchronous flow management system. Improvements in operating costs, reduced lead times, improved delivery performance and quality are highlighted Read More»
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The nature and origin of chaos in manufacturing systems

Beaumariage, T.; Kempf, K.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588235
Publication Year: 1994 , Page(s): 169 - 174

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This paper presents initial efforts to demonstrate chaotic behavior in manufacturing systems, and to explore its origins. We characterize chaotic behavior operationally as small changes bringing about large effects. The manufacturing system studied here by deterministic simulation has only four processing steps and four pieces of equipment. Small changes in this system fall into two categories. We explore changes to policies for the release of raw materials and for the withdrawal of jobs from queues of work in progress, and we investigate changes to the contents and ordering of initial and dynamic queues. Large effects in this system are tracked through changes to throughput time distributions and changes in temporal patterns of finished jobs flowing out of the system. Having shown that small policy or queue changes induce large performance changes, we alter the structure of the manufacturing system to find the origins of the chaotic behavior. This includes the mapping of processing steps onto production machines, the volume of work being added to the system relative to its capacity, and the size of batches being placed into batchable machines. It is shown that each of these factors contributes to the complexity required for the onset of chaotic behavior Read More»
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Computer system design for continuous gas monitoring

Kilinskas, W.A.; Mazzarella, R.B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588260
Publication Year: 1994

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Summary for only given, as follows. The purity of gases used in semiconductor manufacturing have to be continuously monitored to ensure quality control. Gas monitoring systems have been developed and installed at several manufacturing sites for this application. Analytical instruments, sampling systems, and computer systems have been incorporated in these panels to enable continuous monitoring of ultra high purity gases. This presentation describes the computer systems which perform multiple tasks such as analyzer status monitoring. A functional computer design is presented with example of hardware and software implementations. A description of a real time, multitasking STD BUS system is included Read More»
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Particle reduction through the control of triboelectric charges

Ypsilanti, B.; Sanden, B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588205
Publication Year: 1994 , Page(s): 92 - 94

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This study demonstrates the effectiveness of using ion generators to control triboelectric charges as a means of reducing the number of particles that adhere to wafers during the manufacturing process. This study was instituted in a mature wafer fab in order to achieve some level of particle reduction in a short time without the expense and engineering effort associated with minienvironments Read More»
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Principled measurement strategies for a self-directed work team environment

Nguyen, T.T.H.; Cronin, J.J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588183
Publication Year: 1994 , Page(s): 50 - 55

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This paper describes a reproducible and effective process for implementing a measurement/feedback strategy in a newly formed self-directed work team environment at the IBM Microelectronics Division semiconductor manufacturing facility in Essex Junction, Vermont. This is an “Island to Nation” process where the “Nation” (the parent organization) maintains its structure, policies, and norms while the “Island” becomes the experiment. In this island there are roughly 100 people reconfigured from five centrally structured, multi-missioned departments (Project 070) into 12 decentralized, distinctly missioned teams. Discussed are player and coach responsibilities, the changing norms of the organization, the step-by-step process and the principles that underlie each step Read More»
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Integration of automated defect classification into integrated circuit manufacturing

Breaux, L.; Kawski, J.; Singh, B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588279
Publication Year: 1994 , Page(s): 290 - 292

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Comparing various types of minienvironments

Abuzeid, S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588163
Publication Year: 1994 , Page(s): 22 - 25

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The application of minienvironment-based isolation technology for the reduction and control of particulate contamination levels has progressed from the development and evaluation stages to its current status as a preferred alternative for new semiconductor manufacturing facilities. This paper examines various types of minienvironments currently used in existing and new semiconductor manufacturing facilities including, ceiling-hung or ceiling-suspended, self-powered, floor-supported with a fan-filter module, and tool-integrated minienvironments. This paper also examines and compares various parameters affecting the semiconductor manufacturing operations such as ergonomics, flexibility, performance and cost and discusses the integration of minienvironments into the facility Read More»
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Real-time measurement for fast cycle time

Doering, R.R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588282
Publication Year: 1994

IEEE Conferences

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Summary form only given. The most challenging overall goal of the Microelectronics Manufacturing Science and Technology (MMST) Program was the demonstration of 3-day cycle time for manufacturing double-level-metal 0.35-μm CMOS circuits. Achievement of this goal was enabled by development of: (1) a 100% single-wafer processing facility and (2) a substantial implementation of real-time process and factory control. In this paper, we focus on the relationship between cycle time and real-time control Read More»
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Ion implant damage detection by surface photovoltage

Lowell, J.; Wenner, V.; Wagner, D.; Anjum, M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588286
Publication Year: 1994 , Page(s): 316 - 318

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In this paper we report on the application of optical surface photovoltage (SPV) to both quantify and qualify amorphous layers and/or lattice damage due to ion implantation to CZ P-type silicon. We will show how the technique can be used for post-anneal measurement of residual damage Read More»
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Resource efficiency within an integrated 200-mm fabricator

Johnson, G.V.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588267
Publication Year: 1994 , Page(s): 267 - 268

IEEE Conferences

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Survival in the semiconductor business of the 1990's and beyond will be driven primarily by low cost, high quality producers. Key to accomplishing this will be the efficient use of resources-both human and material. IBM's 200-mm semiconductor fabricator in Essex Junction, Vermont, the Apply/Align department has pursued cost reduction by more efficiently using all of its members, from production technicians to entry-level operators. This paper describes the efficiencies derived from the use of Market-Driven Quality (MDQ) teams within the department and across all four Alternate Work Schedule (AWS) shifts. MDQ teams are involved with a wide variety of activities such as cross training, rework and scrap reduction, cost reduction of spare parts, as well as improved tool availability and utilization. The efforts of each team have enabled this department to realize a 13 percent reduction in staffing while increasing output by five percent. The majority of this improvement resulted from cross-training, where individuals within the department were separated into two areas; align and apply, where no one was receiving cross-training. Because of the MDQ team approach the department has been able to implement a cross-training program on all align and apply tools. This has given the team the flexibility it needs to adequately cover vacations, lunch breaks, work breaks and illnesses, as well as realize a significant reduction in staffing. Continuing its efforts to become even more efficient, the department has set an additional seven percent increase in output as its target for year-end 1994 Read More»
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Mini environment systems. Enabling technology for flexible fabs of the future

Baldwin, K.; Castrucci, P.; Williams, M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588155
Publication Year: 1994

IEEE Conferences

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Summary form only given. As the industry moves from one generation of IC technology to the next with smaller and smaller submicron devices and larger and larger wafers, severe constraints will be placed on manufacturing fabs. Conventional fabs typically have four generations of product running at once: advanced technology in development; growing technology ramping-up; current technology at its peak; and one generation declining and going out. Fab flexibility will be a key requirement as technological changes demand substantial tooling changes. We will describe a Minienvironment System that integrates the many tooling and process requirements the “Fab of the Future” Read More»
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Production implementation of a practical WLR program [wafer level reliability]

Garrard, S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588227
Publication Year: 1994 , Page(s): 144 - 146

IEEE Conferences

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Wafer Level Reliability (WLR) programs have been active in many semiconductor companies since the mid 1980's. Test structures are designed to accelerate known reliability failure mechanisms (similar to ET structures for parametric testing). Large samples of these test structures are packaged and tested to determine reliability failure rates. These WLR programs typically focus on electromigration (EM), hot carrier, and TDDB testing of packaged parts. National Semiconductor has developed and implemented a WLR program which differs from the traditional approach. Wafer manufacturing personnel need to know which people, equipment, or process variables need to be better controlled to prevent reliability problems in the field. They also need faster feedback. Our WLR program looked at these issues and designed a more practical approach to eliminating fab-related reliability problems. Wafers, not packaged parts, are tested in-line and at the end of line (before sort test) to provide near-real-time feedback. We identified our top ten reliability failure mechanisms of concern based on past field failure rates and reliability monitors. WLR test structures and test methods were then designed to measure the effect of wafer fab process variability on reliability risk. Designed experiments were used extensively to correlate fab process monitors, WLR test results, and reliability test results Read More»
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Control of interfacial oxide using a novel cluster tool technology

Frystak, D.C.; Albone, J.; Rumaine, P.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588169
Publication Year: 1994 , Page(s): 28 - 33

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Improved control over the undesired oxidation of crystalline silicon surfaces during the steps preceding the polysilicon deposition process can be obtained through clustering of the final oxide removal step with the deposition. Experimental results indicate that the resistance of polysilicon contact structures can be reduced by using a clustered HF-vapor etch/polysilicon deposition sequence in place of conventional wet HF etching followed by polysilicon deposition. Such a process has been shown to reduce the resistance of 0.65 micrometer contacts by 40% relative to that of conventional processing. This improvement is a result of inhibiting the growth of native oxide and is attributed primarily to improved ambient control during the lending step at the beginning of the LPCVD process. Interactions between the settings of the HF-vapor etch process were found to further impact the process. Subsequent tests using polysilicon emitter transistors showed that the cluster tool process sequence resulted in better reproducibility of transistor gain and emitter resistance relative to the conventional process. Details of these experiments are reported Read More»
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Ion beam contamination during P+ source/drain ion implantation

Jacobs, C.; Karnett, M.; Shaw, R.; Pulvirent, L.; Bendall, E.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588257
Publication Year: 1994 , Page(s): 232 - 236

IEEE Conferences

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This paper describes the studies performed to determine whether or not a high energy boron contaminant was being introduced during a BF2, P+ source/drain implant and its impact on critical electrical device parameters and sort yields. The study confirmed the presence of a high energy boron contaminant during P+ implant on a medium current ion implanter. The contaminant significantly altered both PMOSFET threshold voltage and sort yield. While control of source vacuum during P+ implant impacted the degree of contaminant present, it could not be effectively eliminated. A manufacturable solution could only be achieved by introducing a beam filter and controlling source vacuum to effectively eliminate the high energy boron contaminant. Modification of the P+ implant conditions to eliminate the high energy contaminant significantly improved DC parametric and wafer sort yields Read More»
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New technology for old equipment [wet chemical process stations]

Vedaa, N.; Pakulski, M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588253
Publication Year: 1994 , Page(s): 220 - 223

IEEE Conferences

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In September 1992, International Business Machines chose Phoenix Process Automation to upgrade six automated wet chemical process stations at IBM's plant in Essex Junction, Vermont. After five to six years of operation, the stations had reached geriatric status, experiencing excessive downtime, frequent chemical spills, high scrap rates, and reduced throughput. IBM and Phoenix personnel worked closely to plan and implement a comprehensive upgrade program, which included major improvements to hardware and software controls. Today, the upgraded wet stations are delivering significantly improved throughput and yield, with dramatic reductions in equipment downtime, scrap, and chemical spills. The program's success led to four additional upgrades and an ongoing collaboration between Phoenix and IBM to improve wet station reliability and productivity Read More»
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A neural net based, in-line focus/exposure monitor

Tsai, P.; Spanos, C.J.; Nadi, F.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588284
Publication Year: 1994 , Page(s): 305 - 310

IEEE Conferences

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Two parameters that determine the performance of projection steppers for IC fabrication are the defocus distance and the exposure time. Currently, these settings are optimized by visual examination of a test pattern exposed in a matrix of varying focus and exposure settings. An automated approach promises better consistency and reproducibility at a lower cost. In this work we have automated this calibration task by using digital image processing and neural networks. Digital image processing techniques (such as edge extraction and convolution) are used in pre-processing digitized optical images of specific test patterns printed in a 5×5 matrix of varying focus and exposure settings. The results are used to train a feed-forward neural network to recognize the key aspects of the patterns printed under different stepper settings. The trained network takes a single image of a printed test pattern and estimates the actual focus and exposure settings that were used in exposing the test pattern. It can also suggest possible corrections to the focus and exposure settings in order to ensure optimal operation of the stepper. Results show that this method can identify the optimum settings for the stepper. Also, this procedure can be extended to ensure that the exposure and focus settings are optimal on a run-to-run basis in a production environment Read More»
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Evaluating the throughput of cluster tools using event-graph simulations

Nehme, D.A.; Pierce, N.G.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588243
Publication Year: 1994 , Page(s): 189 - 192

IEEE Conferences

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Semiconductor wafer manufacturing equipment, such as cluster-tools and flexible lithography tracks, often contains several process modules combined with one or more wafer handlers. Equipment designers and owners are interested in simulating the throughput of this complex equipment. As an alternative to traditional discrete-event simulations, we have used the event-graph and resident-entity approaches to build a flexible simulator. The simulator was written in C++ (an object-oriented extension to C) and has proven to be easily extendible. Compared with simulators using more traditional approaches and implemented in specialized simulation languages, it runs extremely fast. Execution times are orders of magnitude less, even on low-end hardware with limited memory. Using a built-in, full-factorial experiment generator, we have been able to quickly evaluate many possible equipment configurations. The event-graph approach involves examining the key events in a process, their effect on the state of the system, and their relationship with other events. The events in the model are associated with resident entities (the wafer handlers and process modules) not the transient entities (individual wafers). This enables faster execution, especially in systems with large batch sizes and a large number of wafers. We used the inheritance features of C++ to ease the addition of new types of process models and wafer handlers Read More»
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Process transfer from conventional RIE to transformer-coupled high density plasma metal etch system

Christie, R.; Johnston, S.; Kutchmarik, D.; Barlow, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588171
Publication Year: 1994 , Page(s): 34 - 36

IEEE Conferences

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One of the most challenging processes in semiconductor manufacturing is the dry etching of aluminum alloys in plasma. The requirements include: anisotropy, high selectivity to photoresist, control of critical dimensions, residue free etching, and minimal pattern sensitivity. Along with these requirements, a post etch treatment is needed to prevent the onset of corrosion. In a manufacturing environment, high throughput, minimal down time, and low cost of ownership are essential. IBMs Advanced Semiconductor Technology Center (ASTC) was a beta site for the LAM 9600 metal etch tool. Plasma enhancement, in this system, is achieved using TCP (transformer coupled plasma). With TCP, a high density plasma is generated in a wide pressure range (5 to 100 mTorr) allowing for improved process capabilities. Post etch treatment, on the 9600 system, consists of two parts: a photoresist stripper module and a atmospheric passivation module. This paper will discuss the LAM/IBM ASTC beta site tool install, debug, and process transfer/qualification experience. Electrical data, critical dimensions, particle performance, etch rates, uniformities, selectivities, etch profiles, and tool availability will be compared to the LAM 4608 system Read More»
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Performance results of large field mix-match lithography

Urbano, J.T.; Anberg, D.E.; Flores, G.E.; Litt, L.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588174
Publication Year: 1994

IEEE Conferences

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For an increasing number of semiconductor manufacturers, mix-and-match lithography has grown from a curiosity to an economic necessity. Significant cost of ownership savings can be derived from mix-and-match strategies maximizing the utilization of low to medium cost 1× optical systems for imaging non-critical levels, while high cost reduction or e-beam systems are dedicated to critical levels. Paramount to successful mix-and-match strategy are the resolution and overlay registration of the 1× tools. However, while much can be said about resolution, this discussion will focus on the overlay registration metric. More specifically, data will be presented which illustrates the overlay performance of Ultratech's new generation 1× i-line stepper, the 2244i, to that of an SVGL Microscan reduction stepper Read More»
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Applying constraint management theory in a wafer fab

Villforth, R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588237
Publication Year: 1994 , Page(s): 175 - 178

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This paper reviews National Semiconductor's experience in applying constraint management techniques at an integrated circuit wafer fabrication factory in South Portland, Maine. It explains why constraint management was undertaken and the effect that constraint management techniques have had on product shipments, inventory, cycle times, and due date delivery performance. The process of identifying bottleneck tools, the methods used to increase tool output, and the synchronization of tool output and inventory are described. The effect of factory indices and information systems on employee behavior and the strategies used to convince people to behave differently are also described. The theory of constraint concepts is briefly reviewed Read More»
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Implementing automated equipment performance control in the manufacturing work cell

Pomorski, T.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588233
Publication Year: 1994 , Page(s): 161 - 168

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This paper describes a design and implementation roadmap utilized to establish automated manufacturing equipment controls within the class 100 wafer fabrication area of the National Semiconductor, Data Management Division, South Portland, Maine, facility. The integration of automated equipment controls, including recipe downloads, process parameter verification, and real-time performance monitoring is a key element in the creation of a High Performance Manufacturing Work Cell. The design and implementation of equipment control follows a structured process which ensures alignment with the organization's mission, goals, and core values. The process roadmap begins with the work cell vision and continues through sequential development to a fully functional equipment control implementation. The roadmap also suggests tools and documentation to support the development process. As an integral component in the work cell design, automated equipment performance control offers potential benefits in work cell productivity, product yields, cycle time, and resource utilization. Specific examples of successful equipment control, including interface options for non-SECS compatible equipment, are discussed Read More»
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Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

Hess, C.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588276
Publication Year: 1994 , Page(s): 282 - 289

IEEE Conferences

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To inspect and classify defects occurring during backend process steps, this paper describes a comprehensive methodology how to develop, use, and dimension test structures and how to optimize their organization inside given test chip boundaries. Starting point is the description of process steps and known types of defects. According to existing design rules different test structures will be designed and arranged as (in-line) process monitors inside a checkerboard framework using standard boundary pads Read More»
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A generic model for cluster tool throughput time and capacity

Wood, S.C.; Tripathi, S.; Moghadam, F.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588245
Publication Year: 1994 , Page(s): 194 - 199

IEEE Conferences

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The throughput time within a cluster tool can be approximated as T+lt, where T is the fixed throughput time of the cluster, l is the lot size, and t is the average incremental throughput time resulting from a lot size increase of one wafer. Simulations of different cluster tools are used to illustrate and validate the model. The fixed throughput time (T) consists of both an external component associated with loadlock operations such as loading and pumping, and an internal component resulting from dynamic effects such as congestion in the cluster tool. The expressions for the incremental throughput time (t) includes the wafer handling time, and may include the module processing time. This model predicts that the maximum throughput rate of the cluster tool is 1/t, and that this throughput rate can only be achieved if multiple lots can simultaneously access the cluster tool. The model also predicts that this number of lots must increase, for example, as lot size decreases, the number of identical modules on a cluster increases, or lot loading time increases. This model was applied to a CVD cluster tool at Intel Corporation. The model predicted an increase in the cluster's throughput rate of roughly 10% over current operating practice, if one lot could be loaded while a different lot was being processed. The model was verified using a simulator and then on the cluster tool itself Read More»
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Development of a manufacturable low pressure ROXNOX oxidation process [for CMOS technology]

Bilotta, S.; Proctor, D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588177
Publication Year: 1994 , Page(s): 39 - 49

IEEE Conferences

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Development work was completed on a ROXNOX oxidation to harden the gate oxide against hot carriers. Although device lifetime criteria were met and exceeded, there were serious manufacturing problems which remained. These problems included nonuniform oxide, high particle counts and excessive equipment failures due to the high temperature required for the ROXNOX oxidation process. A series of equipment and process solutions resulted in a factor of 2 film uniformity improvement, a factor of 2 reduction in average particle counts and a reduction of the occurrence and magnitude of particle spikes as well as improvement in equipment availability by 20% Read More»
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SEM/EDS analysis method for bare silicon particle monitor wafers

Sullivan, N.; Arsenault, S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588281
Publication Year: 1994 , Page(s): 293 - 296

IEEE Conferences

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A method for effectively utilizing a Scanning Electron Microscope (SEM) for defect review and identification of unpatterned silicon particle wafers, following inspection on a laser-scanning defect inspection tool, is presented. The method involves pre-patterning of bare silicon wafers at the extreme edges, typically less than 3 mm from the edge of a 200 mm wafer, using standard (I-Line) photolithographic processing. The registration marks created in this process are used for stage correlation between the SEM and laser-scanning wafer inspection tools. Use of these marks is demonstrated to result in a 50% improvement in particle location accuracy (mean+2 sigma) over previously reported results. Further optimizations, including modeling and removal of systematic error sources through data transformations, demonstrate the additional improvements in particle location accuracy that are possible Read More»
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Contamination control in semiconductor industry using laminar barrier inerting technology

Quilantang, E.; Sharif, A.; Hosein, A.; Yokum, T.; Cartwright, R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588214
Publication Year: 1994 , Page(s): 112 - 114

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Laminar Barrier Inerting is a new and effective method of preventing air infiltration into semiconductor process equipment. Air infiltration during loading and unloading is a major source of contamination within semiconductor process furnaces. During these steps, cooler clean room air can replace hot process nitrogen due to buoyant forces. Many fabrication processes are quite sensitive to oxygen and moisture resulting from air infiltration. Praxair has developed, patented (patent number 5,210,959) and tested (in conjunction with Texas Instrument) Laminar Barrier Inerting (LBI) Technology which is capable of keeping oxygen and moisture levels down to ppm levels during furnace operations. With the present practice of having no nitrogen curtain or using certain nitrogen jets, the oxygen and moisture levels inside the furnace reach as high as atmospheric levels. By using Praxair's improved LBI system, the furnace environment is kept clean at all times. Because of this application, the pre-process purge operations performed to clean the furnace can be shortened. In addition, having the process environment continuously controlled reduces product variability. Retrofitting the horizontal thermal reactors with the laminar barrier inerters at the furnace doors could potentially increase their life span. Finally, the LBI system can be used to cool the process wafers and therefore, decrease the growth of native oxide Read More»
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Real time factory monitoring system

Perkett, W.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588265
Publication Year: 1994 , Page(s): 261 - 266

IEEE Conferences

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Currently, the integrated circuit facility is run by a paperless Process Flow Control computer system. This PFC system provides the operator with all the required information about any lots and allows the operator to make keyboard entries to provide feedback of data to the manager. The objective of the real-time factory monitoring system is to use the data collected by the PFC system to determine the following information: (1) machines that are currently down, (2) machines that are at 100% capacity, (3) machines that have been idle for more than 30 minutes, (4) machines that are currently working on nonproduction runs, (5) machines that have caused lots to fail Read More»
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Performance, process architecture, and tooling considerations for advanced semiconductor wafer fabs

Slaby, C.P.; Baker, G.; Castrucci, P.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588154
Publication Year: 1994 , Page(s): 7 - 9

IEEE Conferences

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Results of a study of designing high-performance advanced semiconductor wafer fabs are presented focusing on the underlying process architecture and tooling considerations. Processing framework of 0.35 micron technology suitable for ASIC, microprocessor and SRAM manufacturing is discussed. Results of the modeling and simulation of equipment and fab operation are presented which were used to determine the minimum feasible equipment complement required for the target volume requirements of 500 wafer starts per day. These results confirm that the proposed wafer fab for the 0.35 micron process technology is capable of achieving low-cycle times under 2× of the raw process time or about 1 week of the calendar time. This rapid cycle time is primarily due to the maximum use of the integrated cluster tools Read More»
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Wafer level tracking enhances particle source isolation in a manufacturing environment

Zinke, K.; Abugov, R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588272
Publication Year: 1994 , Page(s): 274 - 278

IEEE Conferences

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The successful manufacture of ULSI integrated circuits at Digital now requires the elimination of particle nucleation sites whose size can be well below the resolution of available on-line defect detection tools. Traditional sequential wafer inspections can often find specific operations which give rise to particles, but they may slow production to unacceptable levels, especially when problems are intermittent. This paper documents a new strategy which combines randomization of wafer order with wafer level tracking and patterned wafer particle detection to detect submicron sources of defects. Case studies illustrate the ability of this method to detect nucleation sites invisible to defect detection systems, and reduce the number of inspections required to trace specific defect sources. Cases where application of this technique should not be used are also provided Read More»
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Plasma process integration for larger wafer manufacturing

Bollinger, L.D.; Gardopee, G.J.; Mathur, D.P.; Mumola, P.B.; Nester, J.F.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588167
Publication Year: 1994

IEEE Conferences

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Summary form only given. We describe a methodology for integrating plasma technology into large wafer manufacturing processes for the purpose of controlling the critical dimensions of those wafers. The Plasma Assisted Chemical Etching (PACE) process is now used commercially to control the Total Thickness variation (TTV) of bulk silicon wafers to &les;0.2 μm and to produce bonded Silicon-on-Insulator (SOI) wafers with active layers having mean thicknesses of 100-nm or less and layer thickness variations well under 10-nm. We will review recent data supporting the ability of the PACE process to achieve this dimensional control on 200-mm bulk Si and bonded SOI wafers Read More»
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In-line FTIR for epitaxial silicon film thickness measurement on an Applied Materials Centura cluster tool

Wang, C.J.; Wise, R.; Shaohua Liu; Haigis, J.; Farquharson, S.; Fowler, B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588256
Publication Year: 1994 , Page(s): 229 - 231

IEEE Conferences

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Wafer fab construction cost analysis and cost reduction strategies: applications of SEMATECH's future factory analysis methodology

Art, D.; O'Halloran, M.; Butler, B.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588160
Publication Year: 1994 , Page(s): 16 - 21

IEEE Conferences

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This paper discusses semiconductor wafer fabrication (fab) factory construction costs as they relate to emerging technologies. The generation of factories studied represents facilities supporting 200 mm wafers, and products utilizing 0.25 micron line-width geometries. An analytical approach to categorizing and evaluating fab costs is presented. A pareto analysis of four recent factories' costs is presented. The organization of fab construction costs into ten useful assemblies is reviewed and explained. Examination of the cost categories shows that of approximately 200 categories, 23 categories account for approximately 60 percent of the overall construction costs. Potential strategies focusing on reducing construction costs are illustrated. The concepts and data for this paper have been developed from SEMATECH's work with Industrial Design Corporation, the engineering firm contracted to provide engineering services on the SEMATECH Facilities Future Factory Design Program Read More»
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Reducing static related defects and controller problems in semiconductor production automation equipment

Rush, J.; Steinman, A.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588206
Publication Year: 1994 , Page(s): 95 - 99

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The trend toward automated manufacturing increases the importance of controlling static charge to eliminate ESD and contamination within equipment. This paper discusses problems, sources and control methods for static charge. It examines methods used to control static charges in semiconductor production tools. Application of air ionizers in production automation are presented Read More»
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Cluster tool wafer handler reliability modeling using top-down and bottom-up methodologies

Ashe, P.D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588264
Publication Year: 1994 , Page(s): 257 - 260

IEEE Conferences

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Brooks Automation produces automated, vacuum substrate-material-handling products for the semiconductor equipment industry. The Brooks Cluster Tool Wafer Handler is the Cluster Tool manufacturer's Central Wafer Handler (CWH) for PVD, CVD, RTP, etch, and other applications used to manufacture semiconductor devices. Since the Brooks CWH is integrated directly into the customer's Cluster Tool, the CWH reliability requirements are dictated by the Cluster Tool reliability requirements. Typically there is not enough time in the design and development phase to empirically determine the actual system reliability (with confidence). Therefore, reliability modeling is used to determine if the reliability requirements have been achieved. “Top down” and “bottom up” modeling are two methods used to estimate the reliability of a complex system, such as the CWH. The top down method uses knowledge of the system's failure modes to generate a system reliability estimate. These failure modes are identified by evaluating the system's functionality at the top level, then proceeding down to the lower level subsystems to evaluate their failure modes. The bottom up method uses knowledge of the system's component failure modes (or failure rates) to generate a system reliability estimate. These failure modes are generated by the component type and application. This document is intended to provide project managers and engineers with a systematic way to estimate the reliability of complex systems when reliability demonstration data is not available. The examples presented in this document focus on the Brooks CWH. In this document the author: 1) presents two reliability modeling methods, top down and bottom up, for developing reliability models for the Brooks CWH; 2) provides step-by-step procedures for creating these models; and 3) explains the appropriate application of these models to the CWH Read More»
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A cross-training concept: one line-one department

French, D.J.; Santerre, D.J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588187
Publication Year: 1994 , Page(s): 59 - 62

IEEE Conferences

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As empowerment migrates to those levels at which decision making takes place, many areas of manufacturing are developing more sophisticated, self-directed work teams to meet today's demand. The manufacturer must produce both quality and quantity while the market demand remains firm. Maximizing tool thruput while minimizing down time plays a key role in this challenge. At IBM's semiconductor fabrication facility in Essex Junction, Vermont, a process line is applying the concept of cross training to all those individuals in its operation. A line-wide, cross-training program is described that eliminates nearly all barriers between various departments members and their tool sets, thus broadening the operator skill base and utilizing available human resources for balancing work in progress (WIP). This program focuses on eliminating non-operator issues at a given tool set and providing tool coverage during breaks and lunch periods to reduce overall tool downtime. It also attempts to achieve a better managed balance of WIP throughout the line by targeting over-wipped and high-capacity tool sets. Increased output is expected from capitalizing on lost opportunity, developing flexibility and improving total line thruput. Improved morale can be expected by offering people the opportunity to enhance their skills, by presenting new challenges, and breaking routines. A cross-training concept qualifies the current skill base of the manufacturing line, keying in on those skills previously acquired outside the present area of responsibility. A team coordinates training, making decisions to move resources according to business needs Read More»
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Using simulation modeling to calculate WIP levels in semiconductor manufacturing

Potti, K.; Bunch, T.; Clark, C.; Wallers, K.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588244
Publication Year: 1994

IEEE Conferences

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Summary form only given, as follows. This paper discusses a modeling approach which is used to support the production control methodology called AMD Kanban System. AMD Kanban System is a simple, visual, self-regulating system for controlling inventory levels at operations within a manufacturing process. These visual signals pull inventory as required from prior steps, thus maintaining line balance while meeting production schedules with minimum work in process. This methodology involves determining the WIP levels at each step or at the beginning of the “linked” steps in the process flow and adjusting them on a periodic basis. Calculating the exact target inventory levels is a challenging task. The inventory levels are currently estimated based on the processing steps included in the link. The methodology presented in this paper addresses the issue of calculating these inventory levels using simulation modeling. A simulation model of three major semiconductor process flows is used as a test bed. The model is adaptable for any time period the user chooses, e.g. a month or a full quarter. The model predicts the bottlenecks in the fab accurately and allows ideal inventory levels at each step in the process flow assigned by the user. The software then reports exactly what quantity of the inventory assigned each step was used during the simulation period. Based on this it is possible to predict the inventory needed at each step. A prototype implementation method is presented Read More»
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Implanted doping profile engineering design for manufacturability

Kau, D.C.; Steeples, K.; Andreoli, M.; Podbevsek, A.; Tower, B.; Bouchard, D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588173
Publication Year: 1994

IEEE Conferences

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Summary form only given. Doping Profile Engineering (DPE) plays a significant role in optimizing the performance of sub-half micron devices in today's densely packed integrated circuits. Profiles have been carefully engineering for: shallow degenerated junctions; highly non-uniform lateral/vertical channel profiles, and (multiple) retrograde profiles for isolation technology. The implanters designed to fulfil the above requirement must be able to perform large angle tilt/twist implant Read More»
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The Fraunhofer Institute for Integrated Circuits: bridging the gap between microelectronics technology and applications

Seitzer, D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588222
Publication Year: 1994 , Page(s): 126 - 129

IEEE Conferences

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The Fraunhofer-Gesellschaft (FhG) is named after a German scientist, researcher and entrepreneur to indicate its combined mission for doing research for and with industry. FhG is a non profit organisation organized in the legal form of an association. Its basis are 47 institutes which are operated as self organizing entities with a common administrative infrastructure. The model is to do research as a part of the scientific community and to transfer this knowledge to industry in a number of ways, by people or by suitable deliverables such as prototypes of products etc. As an example the structure and operation of the Institute for Integrated Circuits is described together with some examples for projects. They indicate that a number of ways can be taken to solve industrial problems by microelectronics, and that know how from systems and applications is required to make microelectronics from a “technology driven” to a “market pulled” operation. The success of FhG as well as of each individual institute is determined by the share of operating budget derived from R&D contracts which is more than 80% in the case of the Institute described Read More»
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Determination of metals impurity concentrations in semiconductor gases

Wong, C.; Amato, A.F.; Brzychcy, A.M.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588250
Publication Year: 1994 , Page(s): 211 - 214

IEEE Conferences

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Monitoring metals concentration in semiconductor gases requires a variety of sampling techniques. The chemical and physical nature of the matrix gas are what determine which method is most appropriate. Due to the non-homogeneity of metals concentrations in the gases and the lack of information corresponding to the exact chemical composition of each metal impurity present, the extraction efficiency of sampling methods is difficult to verify. Therefore, the sampling methods are designed to capture the majority of metals contaminants whether in solid or vapor form. The focus of this paper is to review the current sampling techniques and analytical methods applied to metals determination in semiconductor gases Read More»
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Application of SEMATECH Defect Model to a 0.6 μm process defect reduction

Saha, S.; Mittal, S.; McDonald, C.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588271
Publication Year: 1994

IEEE Conferences

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Summary form only given. This paper will describe the application of the SEMATECH Defect Model for setting equipment level goals for a new 8" process technology at the inception of the process development. The paper will also show how the model validation was made using a similar process and sort yield visual data, how those goals were used to drive equipment team level improvements and resulting die yield impacts. We will also show how the model results can be used to prioritize competing improvement projects for the highest overall output Read More»
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Semiconductor manufacturing: future process challenges

Bakeman, P.E., Jr.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588164
Publication Year: 1994

IEEE Conferences

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Summary form only given. Current advanced generation semiconductor integrated circuits incorporate photolithographic features of 0.5 microns and contain up to five separate wiring levels. This presentation will concentrate on new process technology requirements which must be achieved to advance technology to smaller devices, higher density, lower power consumption, and higher operating speed. Operating voltages are anticipated to decrease from 3.3 volts to 0.5 to 1.0 volts by the end of the century-primarily driven by the need to reduce power dissipation as more and faster circuits are incorporated onto each chip. Some of the changes will involve improving substrate crystalline defect and chemical contamination levels, reducing etch dimension variation due to spacial variations in the process equipment and the patterns being etched, adoption of chemical mechanical polish techniques to provide planar surfaces for use with 0.25 micron lithography patterns, and ultra clean clustered process equipment to permit lower cost manufacturing techniques to be realized Read More»
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Process control approaches using real time harmonic impedance measurements

Reeves, S.; Fullwood, C.; Turner, T.R.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588283
Publication Year: 1994 , Page(s): 298 - 304

IEEE Conferences

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As semiconductor processing requirements evolve to meet the demands of decreasing geometries, new approaches in plasma metrology will be needed to monitor the performance of the equipment and its processes. This performance has traditionally been monitored via Statistical Process Control (SPC) on output parameters such as etch rate and uniformity. These measurements are typically taken on single film wafers which may not be an accurate representation of product. With emerging, non-intrusive, RF sensor technology, equipment and process engineers have access to signals which provide better resolution in determining the health of the equipment. This paper will discuss the relationships between machine settings, real-time RF sensor measurements and the etch rate and uniformity metrics typically used in machine/process qualifications. Run to run control algorithms using the RF sensor measurements will also be presented. Finally, the implications of using RF sensor measurements to provide real-time closed loop control of machine settings will be discussed Read More»
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Ultra-high purity gas distribution systems for sub 0.5 μm ULSI manufacturing

Cheung, S.D.; Jensen, D.L.; Mooney, G.L.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588212
Publication Year: 1994 , Page(s): 107 - 111

IEEE Conferences

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Details from the design, installation, and certification of a novel, zero deadspace, continuous flow, facility gas distribution and monitoring system, and its initial commissioning results are presented. The system as described has been implemented on the N2, O2, He, and Ar supply lines at Digital Semiconductor's Fab 6 in Hudson, MA. Ultra-high purity (UHP) gases supplied via these systems have demonstrated guaranteed performance specifications of <1 part-per-billion (ppb), for individual contaminants, to the tool hook-up point-of-connect (POC). Digital Semiconductor adopted this design to supply ultra-high purity gases to processing equipment in support of three successive generations of sub 0.5 μm ULSI semiconductor development and production. Proposed advantages of the design include reduced contaminant accumulation and intrusion with improved purgability, maintainability, and upset monitoring. Results presented detail system start-up and baselining, including data at tool hook-up POC Read More»
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Manufacturability of vacuum microtubes

Mil'shtein, S.; Kozloff, A.; Therrien, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588268
Publication Year: 1994 , Page(s): 269 - 271

IEEE Conferences

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Vacuum microtubes (VMs), a new breed of vacuum tube electronics and solid state technology, are superior in speed, power, radiation hardness and temperature stability than semiconductor-based diodes and transistors. Electrons generated by cold emission, accelerated by an electric field to a velocity of about 6·108 cm/s, travel very short distances of about 1 μm in VMs. With their extremely short transit time, it is possible for VMs to operate at frequencies approaching hundreds of GHz. State of the art studies have demonstrated a few major drawbacks to reliable operation of VMs, namely, unpredictable position of the emitting spot, fluctuating or insufficient emission current, damage to the emitters by excessive electric field, and fundamental problems in producing arrays of emitters with equally sharp apices. In this study we addressed the spreading of technological parameters, such as work function φ, field enhancement factor β', and emitting area α, and their impact on the operation of a VM. Two designs are discussed. The first design requires low φ on the emitter, and no sharpening or etching (β'=1). The design incorporates low φ regions to localize the emission. We feel that VMs have limited flexibility when designed to operate only by electric field control. Therefore, we propose a second design which operates with a photoemitting cathode for microwave and optoelectronic applications. Using Fowler-Nordheim (F-N) tunneling theory we estimated various manufacturable designs of cold emitter devices and phototubes. Our experimental designs are still not manufacturing prototypes, however; because of their simplicity, they can be produced by almost any semiconductor foundry Read More»
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Proceedings of 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC)


Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588127
Publication Year: 1994

IEEE Conferences

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The following topics were dealt with: future factories; frontiers in process technology; manufacturing improvements through team derived activities; contamination free manufacturing; self-directed work teams; yield and reliability; SECS; simulation and wafer control; cost control; process improvement methodologies; in-line defect detection; characterization and management; metrology Read More»
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Climbing the mountain of change [in semiconductor organizations]

Rose, E.; Odom, R.; Martin-Vega, L.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588217
Publication Year: 1994 , Page(s): 117 - 122

IEEE Conferences

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Semiconductor organizations that want to be successful in the 90's must develop organizational structures that utilize their human resources to the fullest potential. Employees must be empowered to make decisions that in the past were reserved for management. A focus on continuous improvement must be alive and well on the factory floor. The challenge lies in developing effective strategies for change that mesh the technology of the industry with new and creative organizational structures. Effective strategies for managing change must start with a fundamental understanding of the conflict that exists between an organization's need for change and an individual's need for personal security. This paper addresses these issues by describing a successful strategy that has been developed and implemented by Harris Semiconductor in their implementation of self-directed work teams. Issues such as rate of change and psychological and social impacts of change are fused into a four step process that has provided significant assistance to self-directed work teams faced with the challenge of climbing the mountain of change Read More»
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In-fab identification of silicon wafers with clean, laser marked barcodes

Fresonke, D.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588232
Publication Year: 1994 , Page(s): 157 - 160

IEEE Conferences

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All AT&T MOS cleanrooms uniquely identify and track individual wafers in the manufacturing process. Recently, we have developed a new technique to put a laser marked barcode on the front surface of the wafer which adds no detectable particles. The mark itself is an adaptation of the SEMI T1 specification which is popularly referred to as BC412. Unlike the SEMI specification, our BC412 barcode is marked on the top of the wafer during the actual wafer fabrication process. Since the marking is done in the cleanroom, a clean marking technology is absolutely essential. Also the front side mark presents challenges to the barcode readers due to process related surface variations. This paper discusses the reasons for individual wafer tracking and reviews some of the benefits we have seen in practice. We compare the front side, clean barcode to other types of wafer identification techniques. We also discuss the marking technology required for clean marking and the reading technology necessary for front side BC412 Read More»
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Improvements in process yields for a 200 mm wafer fabricator

Ouimet, G.; DeBlois, S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588195
Publication Year: 1994 , Page(s): 75 - 78

IEEE Conferences

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IBM's 200 mm wafer fabricator in Essex Junction, Vermont, Like other semiconductor manufacturers, periodically experienced production losses due to wafers scrapped in process or at final wafer test. Efforts to increase yield by the use of traditional top-down management techniques such as executive directives and problem solving by management with little input from hands-on employees did not result in any sustainable improvement. To remedy the situation, IBM turned to it's employees and their knowledge of the product and the processes used to manufacture that product. Two self-directed work teams, which eventually merged into a single unit, were formed and given responsibility for improving process and electrical test yields. A three-pronged approach to improving process yields was put in place that included in-depth team meetings that discovered reasons why wafers were scrapped and drove activity to fix the problems, stimulated preventive actions through systematic investigation and improvement of process controls for every process area, and created focus on process control and yield problems through an incentive program. This program is still in use today. In-depth team reviews are conducted for all wafers stopped in process because of quality screens. These reviews are attended by team members and representatives from every manufacturing department holding wafers that might be defective. Information from these meetings is shared with a subset of the team that works directly with toolset teams (reactive ion etching, wet cleans, oxidations and diffusions, etc.), to improve preventive measures. Actions taken to prevent process problems are developed from working meetings with every toolset team. Teams are rewarded through an incentive program based on attaining team targets, as well as goals for overall fabricator process yield. This work team approach has resulted in an eighty percent reduction in the scrap rate of wafers in process and at wafer-level functional test Read More»
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Enhancing the semiconductor fab layout process

Plata, J.J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588156
Publication Year: 1994 , Page(s): 11 - 15

IEEE Conferences

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With the dramatically increasing cost of building semiconductor facilities, all aspects of factory design and operation must be evaluated to search for cost reduction opportunities. Enhancing the factory layout process using advanced software tools may be one of those opportunities. SEMATECH's future factory design group is evaluating new software products that attempt to increase the productivity and effectiveness of the layout task and thus increase the value of the factory layout. This article focuses on Texas Instruments' findings as a part of SEMATECH's software beta test. This paper explores new semiconductor fab layout software technology and demonstrates the layout productivity gains and value added to the final layout when it was exercised by Texas Instruments newest 200 mm fab. Additionally, semiconductor layout methodology, metrics, and inherit difficulties are discussed. Emphasis is placed on the software's ability to integrate quantitative and qualitative inputs into the layout process, and provide real time feedback to diverse groups of layout users, dramatically increasing the involvement of the customer and thus the value of the final layout, while decreasing the cycle time in generating an optimized layout. Reference is made to the potential added value to the actual manufacturing operation and process. Extendibility of the layout drawings to aid in the operation and future planning of the fab are discussed Read More»
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Stylus profiler monitors chemical mechanical planarization performance

Reilly, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588289
Publication Year: 1994 , Page(s): 320 - 322

IEEE Conferences

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This paper describes the use of stylus-based surface profilers in advanced semiconductor device manufacturing to monitor chemical mechanical planarization (CMP) performance Read More»
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Overview of automatic defect classification

Bennett, M.H.; Tobin, K.W.; Gleason, S.S.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588270
Publication Year: 1994

IEEE Conferences

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Summary form only given. It's no secret that ever-shrinking circuitry challenges all facets of integrated circuit (IC) processing. Lithography, clean-up, thin film, metallization, metrology, and inspection are all being pushed to accommodate smaller and smaller geometries. The same is true for particles, defects and microcontamination. As device sizes shrink, so does the size of particles or defects that cause chip failure and yield loss. Early particle detection and quick analysis are crucial to successful device fabrication. Unpatterned and patterned wafer defect detection is commonplace, and is accomplished at rapid speed and good sensitivity. However, the manual inspection, review and analysis of defects is a slow, labor intensive step that can be a critical bottleneck in the IC process. Automatic defect classification (ADC) is needed to improve inspection throughput and data integrity. ADC can provide enormous benefits; faster inspection/review, increased throughput, larger sample size, greater classification accuracy, improved classification reproducibility, reduced resource overhead, refocus of staff on troubleshooting and analysis, and reduced test wafer usage by utilizing product wafers. The most fundamental step in the design of an effective ADC system is in the translation of human experience and process knowledge into machine hardware and algorithms. For ADC, the key is developing image analysis algorithms that can be integrated or retrofit to existing defect detection/review tools. Ideally, ADC would be able to deal with both monochrome and color images from common imaging techniques used on defect detection and review tools Read More»
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Effects of microcontaminants in oxygen during gate oxide growth: interfacial effects and device reliability

Beck, S.E.; George, M.A.; Bohling, D.A.; Shemanski, B.J.; McGuire, J.T.; Hames, G.A.; Wortman, J.J.; Lanford, W.A.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588208
Publication Year: 1994 , Page(s): 100 - 106

IEEE Conferences

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The effects of different levels of water, nitrogen, and methane contamination in an oxidation ambient during the production of ultra-thin rapid thermal oxides have been investigated. Careful characterization of the oxidation and argon anneal steps have been performed. High levels of water and hydrogen in these ambients were shown to be generated during the process. Nuclear reaction analysis indicates that the final water level in the oxide depends on the water level in both the oxidation ambient and post-oxidation ambient. Increasing nitrogen concentrations in the oxidation ambient resulted in increased interface trap densities and the frequency of low field breakdown. Initial studies of methane in the oxidation ambient show that it also plays a similar role in oxide degradation Read More»
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Methodologies for supplier partnership and manufacturing implementation of continuous improvement projects

Tripathi, S.; Moghadam, F.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588186
Publication Year: 1994 , Page(s): 56 - 58

IEEE Conferences

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With competition dictating early reduction in product prices, profits can only be enhanced by reducing manufacturing costs as quickly as possibly. This makes it imperative to implement all improvement projects into the manufacturing line with minimal delays. This paper describes how to manage the development and transfer of a new process/hardware set, while ensuring minimum impact to fab output, and while both development and manufacturing fabs are in the middle of an aggressive ramp. Incorporation of unit processes developed at vendor sites into semiconductor manufacturers has always been difficult. Process replication, parts availability, quality and delivery schedules, insufficient documentation and training, are just a few. We describe how we developed the partnership with our supplier to develop a sturdy process/hardware kit. Extensive beta-tests were first performed at the supplier site. Numerous process problems encountered during the beta-site at Intel were resolved with close interaction with the supplier. The development, manufacturing site and supplier worked jointly to proactively eliminate previous problems. The supplier implemented audits and process control of their suppliers' processes, provided an experienced team to travel to both Santa Clara and Ireland for hardware start-up and trained Intel technicians. The improvements reduced the cost of ownership at a unit process by 60% due to an increased throughput of 18%, a 2× defect reduction and a 4× increase in the wafers that can be processed between PMs Read More»
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The role of CIM for the fab of the future and custom IC manufacturing

Cobb, D.; Castrucci, P.; Everton, J.; Schewe, M.; Scoville, J.; Smith, G.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588230
Publication Year: 1994 , Page(s): 150 - 156

IEEE Conferences

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Computer Integrated Manufacturing (CIM) will be vital to the profitable production of future sub-micron memory, logic and analog IC products. Computer technology now makes it possible to monitor and control very complex IC production operations. Without this technology it will not be possible to achieve the cycle times and yields that justify the tremendous investment in new fabrication facilities. The increasing importance of CIM means that it must be considered from the very beginning of the design of a new fabrication facility. This paper describes the results of the CIM portion of a Strategic Future Fab Study-or SFFS for short that was sponsored by an international engineering and construction company (Fluor Daniel) and included 23 industry leading companies. The purpose of the SFFS was to design the fab of the future and to challenge the status quo relating to the design, construction, production systems, and operation of wafer fabrication facilities. Through the partnering effort new and novel approaches were developed and defined to achieve more precise manufacturing control, capacity planning, scheduling, improved processing capability, and overall increased productivity Read More»
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Simultaneous control of multiple nonuniformity metrics using site models and monitor wafer control

Mozumder, P.K.; Saxena, S.; Taylor, K.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588248
Publication Year: 1994 , Page(s): 205 - 210

IEEE Conferences

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Present day semiconductor manufacturing processes are subject to tight specifications. High yields with tight process specifications require proactive, “drive to target”, process control. As the size of the wafer in the semiconductor industry increases, nonuniformity across the wafer becomes a crucial yield limiting issue. Modeling nonuniformity in terms of the equipment settings permits calculation of recipes required to achieve the desired nonuniformity. Models for scaler metrics of nonuniformity, such as standard deviation, or range, do not capture all aspects of the nonuniformity (i.e., shape, symmetry, etc.). In this paper we describe the use of spatial models to quantify various measures of nonuniformity, and a controller to keep the nonuniformities within specifications. A flexible controller, called monitor wafer controller (MWC), has been reported previously for the control of semiconductor processes. Use of spatial models in conjunction with the MWC enables the simultaneous control of multiple nonuniformity metrics. The results of applying the MWC with spatial model to a Plasma Enhanced TEOS (PE-TEOS) deposition process on an Applied Materials Precision 5000 (AMT5000) reactor are presented. The controller has kept the interlevel-dielectric deposition process within specifications for over an year Read More»
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Applying yield impact models as a first pass in upgrade decisions [semiconductor manufacturing]

McIntyre, M.G.; Meitz, J.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588228
Publication Year: 1994 , Page(s): 147 - 149

IEEE Conferences

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Golden nuggets of AMHS modeling and design for semiconductor wafer fabrication

Pierce, N.G.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588246
Publication Year: 1994 , Page(s): 200 - 204

IEEE Conferences

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This paper presents the “golden nuggets” or principles for modeling and designing automated material-handling systems (AMHS) for semiconductor wafer fabrication. Discrete-event simulation, analytical, and spreadsheet models were developed to model the performance, reliability, and cost/benefit of conventional cleanroom material handling including manual and automated systems. The components of a conventional cleanroom material-handling system include an overhead monorail system for interbay (bay-to-bay) transport, work-in-process (WIP) stockers for lot storage, and manual systems for intrabay movement. Suggestions for selecting simulation software and a list of the steps required to develop an AMHS performance model are also presented. One of the most beneficial principles for optimizing AMHS performance is to shorten the distance traveled when transporting lots. The second most beneficial principle is to minimize the congestion of a lot in transport. Both of these principles can be implemented through an effective layout of processing equipment and by using design rules for the effective use of AMHS track options such as turntables and customized track configurations. Examples of track configurations include spine-based, perimeter-based and custom layouts. The reliability of WIP stockers is vital to the overall system reliability, especially in comparison to other components. Several principles of operator behavior are also discussed including operator response times and a subjective work aura radius. These nuggets are useful in determining WIP stocker location and in integrating manual and automated material-handling systems Read More»
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Integration of manufacturing in electrical engineering curriculum at the University of Massachusetts Lowell

Prasad, K.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588198
Publication Year: 1994 , Page(s): 79 - 82

IEEE Conferences

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James B. Francis College of Engineering at UMass Lowell in general, and Electrical Engineering Department in particular, has realized the importance of manufacturability of its designs all along as is evidenced from its curriculum, placement of its graduates, and close ties with the regional industries. Under this proposed initiative however, a number of specific courses will be revised in order to imbibe substantial manufacturing content, along with returning all the pertinent analytical skills needed for succeeding in the real engineering world. The goal is not only to educate the students in fundamentals of EE but to also train them in the latest state-of-the-art technology, in order to make students productive on the job, right from the first day. The industry does not have time and resources to train new hires. We, therefore propose to introduce concepts of Integrated Process/Product Development (IPPD) in the undergraduate curriculum of Electrical Engineering (EE) in all its phases Read More»
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Method for selecting semiconductor process equipment using empowered teams

Gross, C.;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588193
Publication Year: 1994 , Page(s): 71 - 74

IEEE Conferences

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A method is described for enabling self-managed teams of engineers to choose semiconductor process equipment for use in a new sub-half micron, 8" wafer fabrication facility. The selected equipment was required to meet the needs of process development and manufacturing. Process capability, manufacturability, impact on fab start up schedule, supplier support, capital cost, cost of ownership, and risk management issues were considered by the teams during the selection process Read More»
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Achieving high performance teamwork in a semiconductor manufacturing operation

Naguib, H.; Shau-Ron Chen;
Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI
Digital Object Identifier: 10.1109/ASMC.1994.588190
Publication Year: 1994 , Page(s): 63 - 70

IEEE Conferences

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